//==============================================================================
//	File:		$RCSfile: CrossPlatform.rdl,v $
//	Version:	$Revision: 1.2 $
//	Desc:		Cross Platform RDL Example
//	Author:		Greg Gibeling
//	Copyright:	Copyright 2005-2007 UC Berkeley
//
//	This copyright header must appear in all derivative works
//==============================================================================

//==============================================================================
//	Section:	License
//==============================================================================
// Copyright (c) 2005-2007, Regents of the University of California
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
//
//     - Redistributions of source code must retain the above copyright notice,
//         this list of conditions and the following disclaimer. 
//     - Redistributions in binary form must reproduce the above copyright
//         notice, this list of conditions and the following disclaimer
//         in the documentation and/or other materials provided with the
//         distribution. 
//     - Neither the name of the University of California, Berkeley nor the
//         names of its contributors may be used to endorse or promote
//         products derived from this software without specific prior
//         written permission. 
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//==============================================================================

//==============================================================================
//	Section:	CVS Change Log
//==============================================================================
//	$Log: CrossPlatform.rdl,v $
//	Revision 1.2  2007/02/27 02:10:58  sshd_server
//	Created RDL examples from RDLC2 test cases, FLEET and Overlog applications
//	
//==============================================================================

//------------------------------------------------------------------------------
//	Unit:		A
//------------------------------------------------------------------------------
unit {
	instance {
		output bit<32> Out;
	} D;
} A;
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
//	Unit:		B
//------------------------------------------------------------------------------
unit {
	instance {
		instance {
			channel O { In -> G.In };
			input bit<32> In;
			instance {
				input bit<32> In;
				output bit<32> Out;
			} G;
		} F;
		channel P { F.G.Out -> Out };
		output bit<32> Out;
	} E;
	
	channel Q { E.Out -> H.I.In };
	
	instance {
		instance {
			input bit<32> In;
			instance { } J;
			channel R { In -> Out };
			output bit<32> Out;
		} I;
	} H;
	channel S { H.I.Out -> Out };
	output bit<32> Out;
} B;
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
//	Unit:		C
//------------------------------------------------------------------------------
unit {
	instance {
		instance {
			input bit<32> In;
		} L;
	} K;
} C;
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
//	Unit:		Top
//------------------------------------------------------------------------------
unit {
	instance A A;
	instance B B;
	instance C C;
	
	channel N { A.D.Out -> B.E.F.In };
	channel T { B.Out -> C.K.L.In };
} Top;

//------------------------------------------------------------------------------
//	Platform:	Verilog
//------------------------------------------------------------------------------
platform {
	language "Verilog";
	plugin "TestLink" DefaultLink;
	terminal ("TestLink") Terminal;
} Verilog;
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
//	Map:		Map
//	Desc:		Please see the RDLC2 technical report for a diagram showing
//				the hierarchy of units, platforms and maps which are part of
//				this example.
//------------------------------------------------------------------------------
map {
	// We're mapping the unit "Top"
	unit Top Top;
	
	// Nested platform declaration
	platform {
		link V { W.Terminal, X.Terminal };
		
		instance Verilog W;
		instance Verilog X;
	} Platform;
	
	// Nested map declaration
	instance {
		unit A A;
		
		platform Verilog Verilog;
	} Y;
	
	// Nested map declaration
	instance {
		unit B B;
		unit C C;
		
		platform Verilog Verilog;
	} Z;
	
	// Specify mappings from units to submaps
	map Top.A onto Y.A;
	map Top.B onto Z.B;
	map Top.C onto Z.C;
	
	// Specify mappings from ports to terminals
	map Top.A.D.Out onto Platform.W.Terminal;
	
	// Specify mappings from platforms to submaps
	map Platform.W onto Y.Verilog;
	map Platform.X onto Z.Verilog;
} Map;
//------------------------------------------------------------------------------