//==============================================================================
//	File:		$RCSfile: FIFO.rdl,v $
//	Version:	$Revision: 1.4 $
//	Desc:		FIFO RDL Example
//	Author:		Greg Gibeling
//	Copyright:	Copyright 2005-2007 UC Berkeley
//
//	This copyright header must appear in all derivative works
//==============================================================================

//==============================================================================
//	Section:	License
//==============================================================================
// Copyright (c) 2005-2007, Regents of the University of California
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
//
//     - Redistributions of source code must retain the above copyright notice,
//         this list of conditions and the following disclaimer. 
//     - Redistributions in binary form must reproduce the above copyright
//         notice, this list of conditions and the following disclaimer
//         in the documentation and/or other materials provided with the
//         distribution. 
//     - Neither the name of the University of California, Berkeley nor the
//         names of its contributors may be used to endorse or promote
//         products derived from this software without specific prior
//         written permission. 
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//==============================================================================

//==============================================================================
//	Section:	CVS Change Log
//==============================================================================
//	$Log: FIFO.rdl,v $
//	Revision 1.4  2007/03/24 22:41:09  sshd_server
//	Added comment about memory initialization parameter
//	
//	Revision 1.3  2007/02/28 20:47:15  sshd_server
//	Spelling and typo corrections
//	
//	Revision 1.2  2007/02/27 02:10:58  sshd_server
//	Created RDL examples from RDLC2 test cases, FLEET and Overlog applications
//	
//==============================================================================

//------------------------------------------------------------------------------
//	Unit:		FIFO
//	Desc:		A simple FIFO.  Note that the type of the input and output is
//				specified by a parameter, which in conjunction allows this unit
//				to buffer messages of any type without modification to handle
//				specific message types.  It is easy to imagine that this
//				combination of features could be used to build other general
//				purpose units, like arbiters.
//------------------------------------------------------------------------------
unit <Type, Depth, MemType, AWidth> {
	// The input and output ports.  Their type is specified by a parameter,
	// allowing it to be inferred by RDLC2.  Notice also the use of the
	// "opaque" keyword which tells RDLC2 not to generate the standard
	// message marshaling and packing logic, allowing the FIFO to treat the
	// input and output data as a simple bit vector rather than being aware of
	// the actual data type used.
	opaque input $Type Input;
	opaque output $Type Output;
	
	// Create a memory with the specified address width (inferred from the
	// FIFO plugin below) and a data width specified by the port "Input" which
	// the plugin knows how to look up.  Notice that the name of this plugin
	// invocation is "Memory" but the actual plugin is determined by the
	// "MemType" parameter specified through one of the "SetParam" plugin
	// invocations at the bottom of this unit.
	// The third parameter ("" in this case) would allow you to specify the
	// initial contents of this memory.  The string argument should be
	// hexadecimal memory contents, one word per line.  Each line can optionally
	// be prefixed with the address to put that line at, leaving subsequence
	// lines to appear at incremental addresses.  For example, "C0: 0A010101"
	// would write 167837953 to address 192 in the memory, assuming it's
	// approximately 8b by 32b.
	plugin Verilog $MemType<$AWidth, "Input", ""> Memory;
	
	// Create a FIFO width the specified depth.  The second parameter is
	// actually given a value by this parameter, and is the log2(Depth).
	// This plugin is responsible for generating the read and write counters
	// and logic, but it does not connect to any ports or the memory.
	plugin Verilog "FIFO"<$Depth, $AWidth> FIFO;
	
	// Tie the memory, the FIFO control logic and the "Input" and "Output"
	// ports together to make this unit a FIFO.  The parameters to this
	// plugin are the names of the above features (the ports, the memory
	// and the FIFO control logic).
	plugin Verilog "FIFOUnit"<"FIFO", "Memory", "Input", "Output"> FIFOUnit;
	
	// Below are a number of invocations of the "SetParam" plugin which
	// will attempt to set it's two arguments equal.  Notice that these
	// invocations are predicated on the specified platforms.  That is to
	// say only one of these invocations will be active at any given time.
	// This plugin can be used in general to make platform specific
	// decisions.  In the future, a richer mechanism (which doesn't rely
	// on plugins) will probably be provided.
	plugin ::1::Platforms::ModelSim	"SetParam"<$MemType, "ModelSimMemory">	SetMemModelSim;
	plugin ::1::Platforms::XUP		"SetParam"<$MemType, "Virtex2ProMemory">SetMemXUP;
	plugin ::1::Platforms::S3		"SetParam"<$MemType, "Spartan3Memory">	SetMemS3;
	plugin ::1::Platforms::CaLinx2	"SetParam"<$MemType, "VirtexEMemory">	SetMemCaLinx2;
	plugin 							"SetParam"<$MemType, "Dummy">			SetNoMemory;
} FIFO;
//------------------------------------------------------------------------------