#implementation: "synplify"
impl -add synplify -type fpga

#device options
set_option -technology virtex2p
set_option -part xc2vp30
set_option -package ff896
set_option -speed_grade -7
set_option -part_companion ""

#compilation/mapping options
set_option -default_enum_encoding default
set_option -resource_sharing 1
set_option -use_fsm_explorer 0

#map options
set_option -frequency 100.000
set_option -run_prop_extract 1
set_option -fanout_limit 10000
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -update_models_cp 0
set_option -verification_mode 0
set_option -modular 0
set_option -retiming 0
set_option -no_sequential_opt 0
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
set_option -hier_report 1
set_option -island_num_paths 10
set_option -island_global_range 0.5
set_option -island_group_range 0.5

#sequential_optimizations options
set_option -symbolic_fsm_compiler 0

#netlist optimizer options
set_option -enable_nfilter 0
set_option -feedthrough 0
set_option -constant_prop 0
set_option -level_hierarchy 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 1

#VIF options
set_option -write_vif 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#Xilinx_PR attributes
set_option -job Xilinx_PR -add par
set_option -job Xilinx_PR -option enable_run 1

#design plan options
set_option -floorplan ""
set_option -nfilter_user_path ""
impl -active "synplify"